A Peripheral Component Interface Express (PCIe) bus is a type of high speed bus of increasing interest in computing systems. FIG. 1 illustrates two components 105 and 110 which communicate via a PCIe bus 115. Each component 105 and 110 includes a bus interface 120. Bus interface 120 includes a physical layer 125, such as transmitters, receivers, input buffers and other circuits to support the PCIe bus 115. PCIe is a packet-based bus protocol. Data packets are formed in the transaction layer 135 and the data link layer 130. The operation of the physical layer 125, data link layer 130, and transaction layer 135 are described in section 1.5 of the PCI Express Base Specification Revision 1.1 (March 2005) published by PCI-SIG, the contents of which are hereby incorporated by reference. A higher data rate (second generation) version of PCIe having twice the data rate of first generation PCIe is described in the draft standard PCI Express 2.0 Base Specification.
The PCIe standard specifies that a PCIe link between components must have at least one lane 140, where each lane includes a set of differential pairs having one pair for transmission (Tx) and another pair for reception (Rx). That is, each lane has one simplex connection to transmit data to the other side of the link and one simplex connection to receive data from the other side of the link.
A PCIe bus interface 120 may include more than one transmitter/receiver pair. The PCIe standard allows for two or more lanes 140 to be aggregated to increase the bandwidth. A link training and status state machine (LTSSM) configures a set of data lanes as a link. A link between two components that aggregates a total of N lanes is described as a “by-N” link. A first generation of PCIe (“gen1”) by-N link has a bandwidth of 2.5 xN Gbps in both the upstream and downstream directions. The second generation of PCIe (“gen2”) has a xN link with twice the bandwidth, or 5 xN Gbps in both upstream and downstream directions.
As illustrated in FIG. 2, a conventional x N link between two components can also be pictured as being equivalent to two unidirectional data links 210 and 220 between the components to send and receive packets in two different directions. That is, a PCIe x N link has N lanes, which corresponds to a total of N dual simplex links. PCIe permits ×1, ×2, ×4, ×8, ×12, ×16, and ×32 lane widths. As an illustrative example, in first generation PCIe, a single lane has 2.5 Gigabits/second/Lane/direction of raw bandwidth such that a ×8 link has 20 Gigabits/second of raw bandwidth in each direction.
Cards having a PCIe interface are typically known as “PCIe cards.” A computer motherboard has a slot connector (often known as a PCIe slot) for the PCIe card to plug into. Computer motherboards can include different size PCIe slots, such as ×1, ×4, ×8, or ×16 PCIe slots. A PCIe card will physically fit and work correctly in any slot that is at last the same size. PCIe supports “down plugging” in which a PCIe card is plugged into a larger sized slot. Thus a ×4 card will work in a ×16 slot. It is also possible for a slot connector having a large physical size to be wired electrically to utilize a smaller number of lanes. For example, a ×16 slot may be wired as a ×8 slot.
PCIe supports some optional features to assist board designers. For example, PCIe supports lane reversal. In lane reversal, two PCIe interfaces having the same number of lanes may negotiate a reversal of lanes. For example, if both interfaces have 16 lanes, then if one of the interfaces has lanes 0, 1 . . . 15 lane reversal permits a complete logical reversal of the lanes, i.e., the ordering of the lanes is reversed such that physical lane 15 is treated as lane 0. Lane reversal permits a card to be used in a motherboard even though its physical lane connectors have the opposite intended order with respect to the PCIe slot connector.
The Peripheral Component Interface Express (PCIe) protocol specifies rules for two link partners to negotiate a link using training sets. In the training phase, each data lane receives training sets that are used by LTSSM logic. One constraint is that an endpoint lane, such as lane 0 or lane 15 of a ×16 device is mapped to lane 0. That is lane 0 is either the first lane or the last lane. Another constraint is that the total number of lanes is a power of two (e.g., one, two, four, eight, or sixteen). Yet another constraint is that a consecutive set of lanes is selected.
However, PCIe has inherent limitations that limit how cards can be connected on motherboards. In particular, conventional PCIe implementations impose limitations on how lanes can be routed on motherboards. Additionally, conventional PCIe also imposes limitations on how add-in-cards can be used. Therefore, in light of the problems described above the apparatus, system, and method of the present invention was developed.